The present invention relates to semiconductor processing and structures, and more particularly to a method of reducing stacking faults in an epitaxial semiconductor layer overlying another semiconductor region.
Increased operational speed and performance is a continual goal in the design of integrated circuits including complementary metal oxide semiconductor (“CMOS”) circuits. CMOS circuits include both n-type field effect transistors (“NFETs”) and p-type field effect transistors (“PFETs”). Because of the different ways in which NFETs and PFETs operate, performance is most improved in CMOS circuits when conditions under which NFETs and PFETs operate are tailored to the unique characteristics of each type of transistor.
Hybrid orientation technology (“HOT”) refers to a way of manufacturing CMOS circuits in which the NFET has a longitudinal direction (direction of the length of the channel region; i.e., source to drain) aligned with one crystal orientation of a semiconductor substrate and the PFET has a longitudinal direction aligned with a different crystal orientation of the substrate. Higher on-current and faster switching can be achieved in an NFET when the longitudinal direction is oriented in accordance with the <100> crystal orientation, due to the greater mobility of electrons in that crystal orientation. In addition, higher on-current and faster switching can be achieved in a PFET for which the longitudinal direction is oriented in accordance with the <110> crystal orientation, due to the greater mobility of holes in that crystal orientation. Unfortunately, the longitudinal directions of the NFET and the PFET cannot be aligned with these different crystal orientations simply by orienting the NFET and the PFET in the semiconductor substrate in different horizontal directions parallel to the top surface i.e., the major surface of the semiconductor substrate. The <100> crystal orientation is oriented at an angle with respect to a plane in which the <110> crystal orientation runs. Therefore, transistors having these different crystal orientations can only be achieved by fabricating a substrate to include different regions which have these different crystal orientations and fabricating the NFET and the PFET in the different regions.
In the fabrication of some types of transistors, an epitaxial layer is grown over an existing single crystal semiconductor region. Difficulties exist in growing an epitaxial region such that it has a proper and unbroken crystal structure throughout. Stacking faults can occur in the epitaxial layer, typically close to underlying semiconductor region. Typically, stacking faults are locations where a plane of the semiconductor crystal is either inserted as an additional plane where it does not belong, or a plane of the crystal structure is missing. In a particular example, a normal crystal structure of silicon includes a periodically occurring sequence of different types of crystal planes such as ABCABCABC, etc. One type of stacking fault, referred to as an “intrinsic” stacking fault, occurs in a structure such as ABCAB//ABC, in which the crystal plane “C” is missing between the second “B” type crystal plane and the next “A” type crystal plane. Another type of stacking fault, known as an “extrinsic” stacking fault, occurs when an extra crystal plane occurs in the crystal structure in an out of sequence order. For example, an extrinsic stacking fault occurs in a sequence of crystal planes such as ABCA/C/BCABC where the additional crystal plane “C” appears between the crystal planes “A” and “B” which is the normal order.
Various approaches have been tried to reduce stacking faults. Annealing at temperatures, e.g., 950 degrees Celsius, which are normally used to heal epitaxial semiconductor layers and to distribute and settle dopants has proven unsuccessful in removing stacking faults. Prior to the present invention, annealing processes known heretofore have not succeeded in removing stacking faults in epitaxial semiconductor layers.